The present invention relates to crossbar switches, and in particular to a method of operating a crossbar switch having a control logic and n input ports and m output ports, wherein information packets of p different priority levels are routed from said n input ports to said m output ports.
The present invention further relates to a crossbar switch having a control logic and n input ports and m output ports wherein information packets of p different priority levels are routed from said n input ports to said m output ports.
Additionally, the present invention relates to a networking system with at least one crossbar switch.
Crossbar switches are used in high performance computer systems and nodes of electronic networks such as communication networks to route an information packet arriving at an arbitrary input port to a specified output port.
A crossbar switch comprises n input crossbars each of which is assigned to one of said n input ports and m output crossbars each of which is assigned to one of said m output ports. An intersection of an input crossbar with an output crossbar is called crosspoint.
The routing of an information packet within a crossbar switch is controlled by a control logic that keeps track of incoming information packets. The control logic analyses header data of said information packets and stores address information related to said information packets in a buffer system which is reserved for this purpose and is assigned to the control logic.
The payload of said information packets is stored in a separate data buffer system according to said address information maintained by the control logic. Storing said address information and the corresponding payload avoids packet losses e.g. in case of multiple packets requiring to be routed to the same output port.
Advanced crossbar switches can handle information packages of different priorities. This feature ensures that packets with higher priority are routed to a specific output port first, even if packets with lower priority requiring the same output port have arrived at the crossbar switch earlier.
A further advanced feature, which is known as link paralleling, comprises temporarily building a logical input/output port out of several physical input/output ports. The bandwidth of such a logical port is increased by a factor corresponding to the number of physical ports used for link paralleling.
Within state-of-the-art crossbar switches, said buffer system of the control logic comprises buffers which are organized as linked lists or as FIFO-buffers. As already mentioned, the payload is stored in a separate data buffer.
A common approach regarding the buffer system of the control logic is to assign a buffer for storing address information to each crosspoint of the crossbar switch. Though it is possible to provide a single common data buffer for storing the payload of all incoming packets, another variant is referred to for the further explanations. This variant is characterized in that each crosspoint also has a dedicated data buffer for only storing the payload of the information packets referenced by the address information of the corresponding control logic buffer assigned to that crosspoint. The plurality of dedicated data buffers is also referred to as data buffer array in the present disclosure.
The following explanations refer to a single crosspoint of the crossbar switch and the corresponding buffer management.
The linked list buffer mechanism is not favorable since it only allows to read one address entry per cycle which for example is not sufficient for link paralleling. Especially in case of different priorities, traversing the linked list buffer takes too much time.
Using a FIFO-buffer avoids the lengthy operation of traversing the linked list. However, if there is more than one priority level, for each priority an extra buffer must be provided. This, in turn, has another advert effect. For example, if there are g_CRA=32 buffer entries provided in said data buffer for storing the payload of thirty-two information packets, the control logic of a crossbar switch supporting p=8 priority levels requires 8×32=256 FIFO-buffer entries for each crosspoint. Although there must be 256 FIFO-buffer entries provided, solely a maximum of 32 information packets, or their payload, respectively, can be stored by said FIFO-buffer in case of all packets having the same priority.